Error cpu tap not found in jtag chain

Could you tell me what I am doing wrong, or what flaws I should look for? I read other threads where users were asked for IDCODE info, I copied those commands but got 0. Is that my problem (assuming I ran the commands correctly)?

I have connected the J-link to a 20-pin ARM JTAG to 20-pin TI JTAG adapter, then to the target. The cables are a total of about 1 foot long, but I tried 1 khz. The EMU0 and EMU1 pins are floating on the TI adapter.

Thanks

===============================================================

SEGGER J-Link Commander V5.12e (Compiled Apr 29 2016 15:04:36)
DLL version V5.12e, compiled Apr 29 2016 15:03:58

Connecting to J-Link via USB…O.K.
Firmware: J-Link V9 compiled Mar 29 2016 18:46:37
Hardware version: V9.30
S/N: 269303908
License(s): FlashBP, GDB
OEM: SEGGER-EDU
VTref = 3.283V

Type «connect» to establish a target connection, ‘?’ for help
J-Link>connect
Please specify device / core. <Default>: ARM11
Type ‘?’ for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
TIF>
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>1 khz
Device «ARM11» selected.

TotalIRLen = 12, IRPrint = 0x0AD1
TotalIRLen = 12, IRPrint = 0x0AD1

****** Error: CPU-TAP not found in JTAG chain

TotalIRLen = 12, IRPrint = 0x0AD1
TotalIRLen = 12, IRPrint = 0x0AD1

****** Error: CPU-TAP not found in JTAG chain

Can not connect to target.
J-Link>wjc 6
Command 0x6 (Unknown JTAG instruction) successfully written
J-Link>wjd 0,36
returns 0x0
J-Link>wjc e
Command 0xE (IDCODE) successfully written
J-Link>wjd 0,36
returns 0x0
J-Link>

Источник

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- 1
Hi, I have a Netgear R7800 router, with erased bootloader.
I want to get access to its memory, and upload a new firmware (or at least bootloader) to it.

Router’s hardware:
CPU: Qualcomm Atheros IPQ8065, 1.7GHz, 2 cores
Flash: 128 MiB (Micron MT29F1G08ABBEAH4:E)
Architecture: ARMv7 Processor rev 0 (v7l), arm_cortex-a15_neon-vfpv4

The problem is — IPQ8065 is not supported by default, all I got is: ****** Error: CPU-TAP not found in JTAG chain

The Netgear firmware for this router is fully open sorce. You can get it from:
downloads.netgear.com/files/GP….2.62_gpl_src.tar.bz2.zip
This processor is listed as «ipq806x» in U-Boot.

So I was thinking maybe somebody can take the processor parameters from there and add the support of it to JLink?

I tried to add it to «JLinkDevices.xml» file, but with no luck.
I’m new with JTAG and SEGGER, help please.

The J-Link Commander log:

Source Code

Connecting to J-Link via USB…O.K.

Firmware: J-Link V10 compiled Mar 7 2019 15:19:19

Hardware version: V10.10

S/N:

License(s): FlashBP, GDB

OEM: SEGGER-EDU

VTref=1.817V

Type «connect» to establish a target connection, ‘?’ for help

J-Link>connect

Please specify device / core. <Default>: ARM7

Type ‘?’ for selection dialog

Device>?

Please specify target interface:

J) JTAG (Default)

TIF>j

Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect

JTAGConf>

Specify target interface speed [kHz]. <Default>: 4000 kHz

Speed>100

Device «ARM7» selected.

Connecting to target via JTAG

TotalIRLen = 15, IRPrint = 0x0011

JTAG chain detection found 2 devices:

#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP

#1 Id: 0x200110E1, IRLen: 11, Unknown device

TotalIRLen = 15, IRPrint = 0x0011

JTAG chain detection found 2 devices:

#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP

#1 Id: 0x200110E1, IRLen: 11, Unknown device

****** Error: CPU-TAP not found in JTAG chain

TotalIRLen = 15, IRPrint = 0x0011

JTAG chain detection found 2 devices:

#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP

#1 Id: 0x200110E1, IRLen: 11, Unknown device

TotalIRLen = 15, IRPrint = 0x0011

JTAG chain detection found 2 devices:

#0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP

#1 Id: 0x200110E1, IRLen: 11, Unknown device

****** Error: CPU-TAP not found in JTAG chain

Cannot connect to target.

J-Link>

Display All
The post was edited 1 time, last by Kovur (Apr 6th 2019, 2:47pm).
- 2
Hello,

Thank you for your inquiry.
The IPQ8065 is currently not supported by J-Link which is why you don’t see it in the device selection.
FYI the core is a Cortex-A15, not ARM7 (ARMv7 and ARM7 have different meanings). So with a bit of luck connection might work when selecting a generic A15 core type.
But no promises as this is a «Krait» core from Qualcomm which is a custom core which only has some architectural similarities to Cortex-A15.
Due to the lack of public documentation from Qualcomm it is hard to tell if they are really compatible to each other or not.

Kovur wrote:

So I was thinking maybe somebody can take the processor parameters from there and add the support of it to JLink?

Unfortunately the demand for such custom cores that don’t follow Arm standards is extremely low so currently there are no plans to to add support for this specific target device.
However as said before, with a bit of luck the core is similar enough to a generic Cortex-A15 so connection might work out of the box.
For Flash support our open Flash loader interface could be used:
wiki.segger.com/Open_Flashloader

Please understand that we can’t offer any support in this endevour as this custom core type is officially not supported by us.

Best regards,
Nino

Please read the forum rules before posting.

Keep in mind, this is *not* a support forum.
Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
Should you be entitled to support you can contact us via our support system: segger.com/ticket/

Or you can contact us via e-mail.
- 3
First of all — thanks for your answer.

It’s not working with Cortex-A15 either. The log is under spoiler:

So, I have two options left:
1) direct programming of flash with J-Flash SPI program.
2) use open flashloader

The second choice is more complicated, so I’m trying the first option first.

The flash memory chip is: Micron MT29F1G08ABBEAH4
The full datasheet: e2e.ti.com/cfs-file/__key/comm…005.MT29F1G08ABBEAH4E.pdf

The J-Flash SPI doesn’t know this chip, so I trying to add it in the Project Settings.

I’ve attached a screenshot and configuration file.

With the current project settings:
— it seems I can successfully read it;
— I can’t write to it;
— I’m getting the wrong flash ID (FF FF FF), although the command is correct (90h).

Something is wrong with parameters, but I can’t figure it out, due to the lack of experience.
Help, please.

Is it possible to do with J-Flash SPI tool or the Flash loader is the only way?

PS: maybe it will help. There are memory adresses used in that router.
github.com/xieyaxiongfly/Ather…ts/qcom-ipq8065-r7800.dts
Images

MT29F1G08ABBEAH4.png

335.4 kB, 1,609×1,008, viewed 491 times
The post was edited 1 time, last by Kovur (May 9th 2019, 3:47pm).
- 4
Hello,

Regarding the failing A15 connection sequence. It actually looks better than expected. Most components are detected so general communication to the core is working.
But what is missing is the core debug register which could not be autodetected.
This can be added manually by the user via a JLinkScript and defining the missing ROM table entries manually.
Ideally this is described in the public target device user manual.

Regarding J-Flash SPI, this tool is intended to work with NOR Flashes mostly.
The Flash you are using is a NAND Flash. The problem with NAND Flashes is that they require lots and lots of use case specific special handlings which the J-Flash SPI software was not created for.
But you could use our J-Link SDK to create your own version of J-Flash SPI which can handle the specific handlings needed for the NAND you are using.
More information about the SDK can be found here:
segger.com/products/debug-prob…nk/technology/j-link-sdk/

All our J-Link software tools have been created by using the SDK.
Alternatively you could try to use the open Flash loader interface. But in this case you need a working debug connection to the target device first.

Best regards,
Nino

Please read the forum rules before posting.

Keep in mind, this is *not* a support forum.
Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
Should you be entitled to support you can contact us via our support system: segger.com/ticket/

Or you can contact us via e-mail.

Источник

Based on the information you provide. SCR1 supports with OpenOCD stack only.
Please skip Ozone 2.61c tool issue, because it uses JLinkGDBServer.

However I try to use JLink + OpenOCD. It is still not working properly.
I can not halt CPU.

Below are detail log

ps: Using olimex ARM-USB-TINY-H + OpenOCD is okay.

sudo ./openocd -s ../tcl -f ~/openocd/tcl/interface/jlink.cfg -f ~/sc-riscv64-unknown-elf-gcc-20180126-linux64/openocd/tcl/target/syntacore_riscv32_v2.cfg

=======================================================
Open On-Chip Debugger 0.10.0+dev-01006-gbc11293 (2017-12-04-16:11)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
init_targets
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
adapter speed: 2000 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain connect_deassert_srst
Info : auto-selecting first available session transport «jtag». To override use ‘transport select ‘.
scr.cpu
Info : No device selected, using first device.
Info : J-Link V9 compiled Oct 25 2018 11:46:07
Info : Hardware version: 9.10
Info : VTarget = 3.275 V
Info : clock speed 2000 kHz
Info : JTAG tap: syntacore_riscv32_v2.cpu tap/device found: 0xdeb01001 (mfg: 0x000 (), part: 0xeb01, ver: 0xd)
Info : IDCODE=0xDEB01001 DBG_ID=0x00820000 BLD_ID=0x18110700
Info : Listening on port 3333 for gdb connections

===================================================================

telnet localhost 4444

Connected to localhost.
Escape character is ‘^]’.
Open On-Chip Debugger

targets
TargetName Type Endian TapName State

0* scr.cpu syntacore_riscv32_v2 little syntacore_riscv32_v2.cpu running

targets scr.cpu
halt
Target not halted
in procedure ‘target’
targets
TargetName Type Endian TapName State

0* scr.cpu syntacore_riscv32_v2 little syntacore_riscv32_v2.cpu running

targets
TargetName Type Endian TapName State

0* scr.cpu syntacore_riscv32_v2 little syntacore_riscv32_v2.cpu running

halt
Target not halted
in procedure ‘target’
DBG_STATUS == 0xE00300DC
Lock detected: 0xE00300DC
========= Try to unlock ==============
DBG_STATUS == 0xA00300DC
Lock with lock_context=0x00000034 repaired: 0xA00300DC
Hart errors detected: 0xA00300DC
Core status: 0x800000C0

Источник

Понятия не имею, никогда не получал такого сообщения. Версии следующие:

1) Проблемы с подключением (вероятно замыкание TDI и TDO?)

Нет никакого замыкания. Все нормально. Соответствует схеме.

2) Включена защита в процессоре (сотрите его ножкой Erase)

Как это?

3) Дохлый процессор

Микроконтроллер рабочий. Залитая родимая прошивка(эмулятор мыши) работает.

4) Дохлый J-Link

J-Link работает. Покупной. Думаю все ОК. Правда не тестил на других отладочных платах. Вот что выдает J-Link Commander

SEGGER J-Link Commander V4.02 (‘?’ for help)

Compiled Jan 13 2009 20:12:59

DLL version V4.02, compiled Jan 13 2009 20:12:45

Firmware: J-Link compiled Jul 30 2008 11:24:37 ARM Rev.5

Hardware: V5.00

S/N : 11111117

VTarget = 3.287V

Info: TotalIRLen = 3, IRPrint = 0x01

WARNING: No matching core found. Selecting default core (ARM7).

****** Error: Too few devices on the JTAG bus. IRPos: 0, TotalIRLen: 3

Could not find supported CPU core on JTAG chain

Found 1 JTAG device, Total IRLen = 3:

Id of device #0: 0x00000000

JTAG speed: 5 kHz

J-Link>

Я думаю, что есть какие-то проблемы с JTAGSEL. Зачем он и как с ним работать. На сайте пишут кое что о этой проблеме, но не понимаю зубоскальский. Хелп плз.

Scheme_AT91SAM7S_board.pdf

Источник

1 / 1 / 1

Регистрация: 20.03.2017

Сообщений: 121

Не могу прошить МК

22.01.2018, 19:32. Показов 13232. Ответов 7

Здравствуйте. Хочу освоить программирование МК. Есть плата с контроллером STM32F103C8T6.Отладчик JetLink9. Человек, разбирающийся в этой теме, любезно предоставил плату с уже работающей мигалкой. В Keil uVision5 пытаюсь перепрошить МК. Но у меня не получается. В окне Options for Target отмечаю use J-Link/J-Trace. Затем нажимаю Start/Stop Debug Session. В ответ получаю сообщения: No Cortex-M Device found in JTAG chain. Please check the JTAG cable and the connected devices и Error: Flash Download failed-Target DLL has been cancelled. Драйвер вроде нормально установился. По крайней мере в диспетчере устройств отображается J-Link driver. Что я делаю не так?

__________________
Помощь в написании контрольных, курсовых и дипломных работ, диссертаций здесь

873 / 534 / 175

Регистрация: 30.07.2015

Сообщений: 1,739

22.01.2018, 20:28

lipton_v, скинь скрины окон Options-for-taget ->debug, Options for target->Debug->settings, и Options-for target->Utilities.

1 / 1 / 1

Регистрация: 20.03.2017

Сообщений: 121

23.01.2018, 05:42

[ТС]

Не такая

873 / 534 / 175

Регистрация: 30.07.2015

Сообщений: 1,739

23.01.2018, 09:22

Сообщение было отмечено lipton_v как решение

Решение

lipton_v, попробуй:
1) поставить SWD во вкладке Port(это не обязательно, но попробуй, хз какая у тебя схемотехника платы) в Options for target->debug-> settings. Если устройство будет норм подключено оно отобразится в поле JTAG Device Chain.
2)Также поставь галки в поле Download options.
3)Убери галку Use debug driver в Utilites
4)Выбери устройство для Debug — J-LINK(выбор отладчиков появится как галку уберешь)
5) зайди в settings и выбери свой целевой контроллер.
И посмотри по схемотехнике, не нужно ли на плату внешнее питание подавать

1961 / 1275 / 130

Регистрация: 04.01.2010

Сообщений: 4,607

23.01.2018, 09:52

Сообщение от _SayHello

попробуй:

поддерживаю. Еще добавлю — можно попробовать поставить по-ниже частоту общения. 5МГц иногда много. Мой JTAG работал на 1МГц.

1280 / 1186 / 175

Регистрация: 02.12.2013

Сообщений: 4,884

23.01.2018, 11:05

И еще добавлю, а драйвер J-LINK ставили?

1 / 1 / 1

Регистрация: 20.03.2017

Сообщений: 121

23.01.2018, 16:16

[ТС]

Ура! Получилось! Спасибо всем, кто не остался равнодушным!

Источник

17th April, 2015, 01:51 AM

#16

I use A0-A22 but I make 2 readings. One with A23 at grround and second with A23 at 3.3v. Can you post the omap jlink project?
17th April, 2015, 01:54 AM

#17

Originally Posted by zalupentiy

Correct way. Need change 3 chips.

Can you tell what chips need to be changed?
8th December, 2015, 02:34 PM

#18

Originally Posted by zzz28

I READING FLASH MEMORY JTAG (JLINK) !!!!

Hi,
How did you conect and read OMAP5948+S29GL256N(BGA), can you share any info or pictures? I also have J-link
Thanks
20th December, 2015, 07:02 PM

#19
9th January, 2016, 04:28 PM

#20

Newbie

Originally Posted by zzz28

I READING FLASH MEMORY JTAG (JLINK) !!!!

I also interested in this question… read OMAP5948+S29GL256N(BGA) — J-link. I can’t read the memory…
13th January, 2016, 07:16 PM

#21

Newbie

Originally Posted by nic2015

I also interested in this question… read OMAP5948+S29GL256N(BGA) — J-link. I can’t read the memory…

Yes and I read… FLASH MEMORY JTAG
14th January, 2016, 06:28 PM

#22
2nd March, 2016, 02:53 PM

#23

Newbie

Hello,

I have a problem with my 8S7T 18K931 AD (Travelpilot FX) Unit. I had removed the SPANSION S29GL256N… BGA Flash Chip for reading a dump but after soldering it back, the UNIT doesn’t start.

Is there a security area at the chip which can only be read via JTAG and doesn’t extern?
I do BGA soldering and so on for so many years now but I can’t explain why the Unit doesn’t start after putting back the chip.Has anyone a dump for it?
Thanks a lot.Best Regards,
8th April, 2016, 11:43 AM

#24

Newbie

Friends,
I have problems to connect OMAP5948GXF with J-link. I tried various configuration settings in J-flash v5.12, but every time i have error when try connect to target: »CPU-TAP not found in JTAG chain». Many times I have checked right JTAG connection to board and 3.3V to VTref from board I applied to.

Maybe someone have project file (*.jflash) with right configuration?

Ford Travelpilot
8M5T 18K931 GD
7 612 300 546
3A054699185187

Thanks!Ford_OMAP_JTAG.JPG
8th April, 2016, 12:41 PM

#25

Originally Posted by Carlos07

Friends,
I have problems to connect OMAP5948GXF with J-link. I tried various configuration settings in J-flash v5.12, but every time i have error when try connect to target: »CPU-TAP not found in JTAG chain». Many times I have checked right JTAG connection to board and 3.3V to VTref from board I applied to.

Maybe someone have project file (*.jflash) with right configuration?

Ford Travelpilot
8M5T 18K931 GD
7 612 300 546
3A054699185187

Thanks!Ford_OMAP_JTAG.JPG

if you require code try 8409
The Following 3 Users Say Thank You to smoggy For This Useful Post:

Carlos07 (8th April, 2016), CustomCars (12th October, 2016), shooting (8th April, 2016)
8th April, 2016, 01:24 PM

#26

Newbie

Thank you smoggy, this is right code!
But i have other problem, unit can’t turn on, and i need replace Spansion bga memory chip, but before doing this i need download full dump from it.
6th May, 2016, 12:49 PM

#27

Junior Member

Originally Posted by tehnosoftex

And what are these problems? Ive seen several units which didn’t start any more, and if I heat up the flash and I power up the unit while the flash is still hot the unit start and run ok. If I remove the power , and apply again when the bga is could the unit is dead again.
I think the flash can be read with jlink but need a proper project. Ive tried to make a project and manage to read only some blocks of flash but the program is disconnecting often. I manage to read and write the flash with a programmer used for jailbreak the PS3, progskeet, but need allot of wires to connect.

I have purchased new GL256N Chips now. But I did not have the original Dump from this chip. Can somebody sell a dump to me?
25th May, 2016, 08:46 AM

#28

Junior Member

Code for Ford FX

Hi have a ford fx navi bought from ebay. But no code can somebody help me

8v4t 18k931 af
881 c7e3a0594 9 9145762

Thanks
25th May, 2016, 08:48 AM

#29

Originally Posted by shorttrader

Code for Ford FX

Hi have a ford fx navi bought from ebay. But no code can somebody help me

8v4t 18k931 af
881 c7e3a0594 9 9145762

Thanks

Your code is 6666

wbr

—————————————————————————————————————————-

Don’t confuse «Standing on my Shoulders» with «Treading on my Toes» ..
The Following 2 Users Say Thank You to shooting For This Useful Post:

REZON (25th May, 2016), sanixmen (25th May, 2016)
25th May, 2016, 09:22 AM

#30

Junior Member

Originally Posted by shooting

WOW — thats great. Works fine. But system is faulty. no navi can turned on no radio. I think there is something else worse. ~~~~

Thanks for your fast help

Do u know what there can be wrong too?? I can switch on. enter code but not more. display on. CD rotating but no sound etc.

Источник

dhananjay.sutariya: Posts: 41; Joined: Thu Feb 28, 2019 12:21 pm

ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

Hi all,
I’m trying to debug my ESP32 through JTAG interface .My debug module which is used is FT2232HL.
After following all the steps that are mentioned thoroughly on this link:
https://docs.espressif.com/projects/esp … ng-openocd

As i go towards, Running OpenOcd i’m getting the following error:
bin/openocd -s share/openocd/scripts -f interface/ftdi/esp32_devkitj_v1.cfg -f board/esp-wroom-32.cfg
Open On-Chip Debugger v0.10.0-esp32-20190313 (2019-03-13-09:52)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 20000 kHz
Info : Configured 2 cores
esp32 interrupt mask on
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : ftdi: if you experience problems at higher adapter clocks, try the command «ftdi_tdo_sample_edge falling»
Info : clock speed 20000 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: esp32.cpu0: IR capture error; saw 0x00 not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Listening on port 3333 for gdb connections
rbin/openocd -s share/openocd/scripts -f interface/ftdi/esp32_devkitj_v1.cfg -f board/esp-wroom-32.cfg
Open On-Chip Debugger v0.10.0-esp32-20190313 (2019-03-13-09:52)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 20000 kHz
Info : Configured 2 cores
esp32 interrupt mask on
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : ftdi: if you experience problems at higher adapter clocks, try the command «ftdi_tdo_sample_edge falling»
Info : clock speed 20000 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway…
Error: esp32.cpu0: IR capture error; saw 0x00 not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Listening on port 3333 for gdb connections

Please Help me solve this issue.

Best Regards,
Dhananjay Sutariya

ESP_Sprite: Posts: 7336; Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

Postby ESP_Sprite » Tue May 21, 2019 1:42 am

Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.

Check your hardware, there’s probably something wrong there. Also, make sure that whatever code is running on your ESP32 doesn’t reconfigure the JTAG pins for other use.

dhananjay.sutariya: Posts: 41; Joined: Thu Feb 28, 2019 12:21 pm

Re: ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

Postby dhananjay.sutariya » Tue May 21, 2019 6:20 am

ESP_Sprite wrote: ↑

Tue May 21, 2019 1:42 am

Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.

Check your hardware, there’s probably something wrong there. Also, make sure that whatever code is running on your ESP32 doesn’t reconfigure the JTAG pins for other use.

Hi ESP_Sprite,
The program on my chip is Blink one.
Blinking GPIO placed on GPIO Num 2.
Still i’m gettiing this error.

Thanks,
Dhananjay Sutariya

dhananjay.sutariya: Posts: 41; Joined: Thu Feb 28, 2019 12:21 pm

Re: ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

Postby dhananjay.sutariya » Wed May 22, 2019 1:01 pm

ESP_Sprite wrote: ↑

Tue May 21, 2019 8:26 am

Then I suggest you check your hardware, as the OpenOCD output suggests

Hi ESP_Sprite,
I have managed to check with my hardware pins allthough i’m getting these errors after that:

bin/openocd -s share/openocd/scripts -f interface/ftdi/esp32_devkitj_v1.cfg -f board/esp-wroom-32.cfg
Open On-Chip Debugger v0.10.0-esp32-20190313 (2019-03-13-09:52)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 20000 kHz
Info : Configured 2 cores
esp32 interrupt mask on
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : ftdi: if you experience problems at higher adapter clocks, try the command «ftdi_tdo_sample_edge falling»
Info : clock speed 20000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0xfffff4e5 (mfg: 0x272 (Tensilica), part: 0xffff, ver: 0xf)
Warn : JTAG tap: esp32.cpu0 UNEXPECTED: 0xfffff4e5 (mfg: 0x272 (Tensilica), part: 0xffff, ver: 0xf)
Error: JTAG tap: esp32.cpu0 expected 1 of 1: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0xffffffff (mfg: 0x7ff (<invalid>), part: 0xffff, ver: 0xf)
Warn : JTAG tap: esp32.cpu1 UNEXPECTED: 0xffffffff (mfg: 0x7ff (<invalid>), part: 0xffff, ver: 0xf)
Error: JTAG tap: esp32.cpu1 expected 1 of 1: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Error: Trying to use configured scan chain anyway…
Warn : Bypassing JTAG setup events due to errors
Info : Listening on port 3333 for gdb connections

ESP_Sprite: Posts: 7336; Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

Postby ESP_Sprite » Thu May 23, 2019 1:53 am

In particular, show down your adapter. » adapter speed: 20000 kHz» means it’s running at 20MHz now.

dhananjay.sutariya: Posts: 41; Joined: Thu Feb 28, 2019 12:21 pm

Re: ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

Postby dhananjay.sutariya » Fri May 24, 2019 5:36 am

ESP_Sprite wrote: ↑

Thu May 23, 2019 1:53 am

In particular, show down your adapter. » adapter speed: 20000 kHz» means it’s running at 20MHz now.

Hi ESP_sprite,
My device’s hardware confiuration have been met . Thanks, yet i’m having some issue here:
xtensa-esp32-elf-gdb -x gdbinit build/blink.elf
GNU gdb (crosstool-NG crosstool-ng-1.22.0-80-g6c4433a) 7.10
Copyright (C) 2015 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type «show copying»
and «show warranty» for details.
This GDB was configured as «—host=x86_64-build_pc-linux-gnu —target=xtensa-esp32-elf».
Type «show configuration» for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type «help».
Type «apropos word» to search for commands related to «word»…
Reading symbols from build/blink.elf…done.
0x400e3406 in _Unwind_RaiseException_Phase2 (exc=0x0, context=0x400d1698 <esp_register_freertos_idle_hook_for_cpu+48>)
at /builds/idf/crosstool-NG/.build/src/gcc-5.2.0/libgcc/unwind.inc:62
62 /builds/idf/crosstool-NG/.build/src/gcc-5.2.0/libgcc/unwind.inc: No such file or directory.
JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
esp32: Debug controller 0 was reset (pwrstat=0x5F, after clear 0x0F).
esp32: Core 0 was reset (pwrstat=0x5F, after clear 0x0F).
esp32: Debug controller 1 was reset (pwrstat=0x5F, after clear 0x5F).
esp32: Core 1 was reset (pwrstat=0x5F, after clear 0x5F).
Target halted. PRO_CPU: PC=0x5000004B (active) APP_CPU: PC=0x00000000
esp32: Core 0 was reset (pwrstat=0x1F, after clear 0x0F).
Target halted. PRO_CPU: PC=0x40000400 (active) APP_CPU: PC=0x40000400
Hardware assisted breakpoint 1 at 0x400d21c4: file /home/dhananjay/esp/blink/main/blink.c, line 139.
Detected debug stubs @ 3ffb26f8 on core0 of target ‘esp32’

Thaks,
Dhananjay Sutariya

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ESP32 JTAG debugging is not functioning properly, OpenOCD is giving these error.

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